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Rethinking Collective Communication for CPU–GPU–DPU Heterogeneous Systems
HCCL is a next-generation collective communication framework designed for multi-rail, multi-accelerator, and DPU-enabled HPC & AI systems.
HCCL is a next-generation collective communication framework designed for multi-rail, multi-accelerator, and DPU-enabled HPC & AI systems.
Designed by PADSYS Lab at University of Florida
Why HCCL?
Traditional collectives assume homogeneous nodes and devices
NCCL/MPI does not deeply model:
DPU/SmartNIC offloading
Heterogeneous capabilities
Multi-rail topologies
Hierarchical AI workloads
Large-scale LLM training exposes:
Cross-device imbalance
Congestion
Inefficient gradient aggregation
Core Design Principles
Core Design Principles
Heterogeneity-aware scheduling
Multi-rail path optimization
DPU-/SmartNIC offloaded computation and reduction
Topology-aware collective decomposition
Performance modeling guided selection (LogGP-based)
Effort 1
Effort 1
A description of an effort and why it matters
Effort 2
Effort 2
A description of an effort and why it matters
Effort 3
Effort 3
A description of an effort and why it matters
Effort 4
Effort 4
A description of an effort and why it matters
Questions?
Questions?
Contact [email] to get more information on the project
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